1. Field
This disclosure relates generally to semiconductor devices, and, more specifically but not exclusively, to determining the age of a semiconductor device.
2. Description
As a semiconductor device ages, the reliability of internal components begins to diminish. The semiconductor device ages during operational use during which the internal components are exposed to varying operational temperatures and voltages. In fact, the effects of aging are proportional to the cumulative temperatures and voltages experienced during use. Thus, internal components which operate at higher temperatures and voltages age faster and deteriorate quicker than those components experiencing more moderate temperatures and voltages.
One such aging effect is Hot Carrier Degradation. Hot Carrier Degradation results when charge carriers become trapped within the gate oxide of a transistor. The trapped charge carriers accumulate over time, creating a built-in charge within the gate oxide of the transistor. This trapped charge decreases the carrier mobility across the channel of the transistor and alters the transistor threshold voltage (“VTH”). Hot Carrier Degradation is aggravated by elevated operating temperatures and voltage, and has a cumulative effect proportional to age. Negative-type metal oxide semiconductor (“NMOS”) components are particularly susceptible to Hot Carrier Degradation.
Another such aging effect is Negative Bias Temperature Instability (“NBTI”). The NBTI mechanism is an electrochemical reaction that involves the electric field, holes, silicon-hydrogen bonds, and temperature. During operation, DC bias voltages generate interface traps between the gate oxide and silicon substrate of a transistor. These interface traps accumulate over time and have the effect of shifting the VTH and reducing drive current. Positive-type metal oxide semiconductor (“PMOS”) devices particularly suffer from the NBTI effect.
Accordingly, different internal components of an integrated circuit have varying reliable lifetimes. These reliable lifetimes are dependent upon localized environments subjected to localized operational voltages and temperatures and upon the specific stress history of the circuit component. Components residing in high-use, high-stress environments will have shorter reliable lifetimes.
One approach to measuring the age of a circuit component in a semiconductor device is based on complementary metal oxide semiconductor (“CMOS”) based oscillator circuits located in proximity of the circuit component. A pair of oscillators, one configured to leave no voltage stress across the PMOS transistors when disabled and the other with PMOS transistors stressed when disabled. The pair is designed to be as similar as possible so their oscillation periods will match closely. The unstressed oscillator serves as an in situ reference, providing an effective measure of temperature and supply voltage during tests before and after stress. Measurements of the reference oscillator can be used to correct for different voltages and temperatures during pre and post stress tests. Using the state-of-the-art CMOS processes, oscillator periods will typically vary about 1% for a 10 mV supply change and 1% for 10° C. change in temperature. Aging effects for oscillators are expected to be in the range of a few percent over the lifetime of a product. Accelerated life tests used to measure the aging effect may only show a few percent change in period depending on the voltage, temperature, and duration of the experiment. Because the change of oscillator periods is so small even during the lifetime of the circuit component, it is desirable to have a different aging monitor circuits whose characteristics change more substantially than a CMOS based oscillator circuit over time.